/*
 * system-ss805x-priv.h
 *
 * The private definitions for system-ss805x.c.
 * Under normal conditions, it CAN be ignored by reader.
 *
 * Copyright (C) 2024 Sinh Micro, Inc.
 * Subject to the GNU Public License, version 2.
 *
 * Author: lixiang<lixiang@sinhmicro.com>
 * 
 * Encoding format: GB2312
 * Version: v1.2.2
 * Date: 2024-11-05
 */

#ifndef __SYSTEM_SS805X_PRIV_H__
#define __SYSTEM_SS805X_PRIV_H__

#include "hal-config.h"

#if (CONFIG_SYS_SCLK_SRC == 1)          /* HIRC, 12MHz */
    #define CLKCON_VAL          (0x01)
    
    #if (CONFIG_SYS_SCLK_DIV <= 4)
        #define RCCON_VAL     (((CONFIG_SYS_SCLK_DIV - 1) << 4) | 1)
    #elif (CONFIG_SYS_SCLK_DIV == 6)
        #define RCCON_VAL     ((4 << 4) | 1)
    #elif (CONFIG_SYS_SCLK_DIV == 8)
        #define RCCON_VAL     ((5 << 4) | 1)
    #elif (CONFIG_SYS_SCLK_DIV == 16)
        #define RCCON_VAL     ((6 << 4) | 1)
    #elif (CONFIG_SYS_SCLK_DIV == 32)
        #define RCCON_VAL     ((7 << 4) | 1)
    #else
        #error("invalid CONFIG_SYS_CLK_DIV!")
    #endif

    #if (CONFIG_SYS_SCLK_DIV == 1)      // 12MHZ, wait 3 cycle, 3MHz
        #define CKCON_VAL       (0x31)
    #elif (CONFIG_SYS_SCLK_DIV == 2)    // 6MHz,  wait 2 cycle, 3MHz
        #define CKCON_VAL       (0x11)
    #else                               // others, wait 1 cycle
        #define CKCON_VAL       (0x01)
    #endif
#elif (CONFIG_SYS_SCLK_SRC == 0)        /* LORC, 32KHz */
    #define CLKCON_VAL          (0x00)
    #define RCCON_VAL           (0x00)
    #define CKCON_VAL           (0x01)
#else
    #error("invalid CONFIG_SYS_SCLK_SRC!")
#endif

/*
 * setup the delay count value
 */
#if (CONFIG_SYS_SCLK_SRC == 1)          /* HIRC, 12MHz */
    #if (CONFIG_SYS_SCLK_DIV == 1)      // 12MHZ, wait 3 cycle, 3MHz
        #define DELAY_MS_CNT    (300)
        #define DELAY_10US_CNT  (13)
    #elif (CONFIG_SYS_SCLK_DIV == 2)    // 6MHz,  wait 2 cycle, 3MHz
        #define DELAY_MS_CNT    (203)   // TODO
        #define DELAY_10US_CNT  (10)    // TODO
    #elif (CONFIG_SYS_SCLK_DIV == 3)    // 4MHz
        #define DELAY_MS_CNT    (270)   // TODO
        #define DELAY_10US_CNT  (13)    // TODO
    #elif (CONFIG_SYS_SCLK_DIV == 4)    // 3MHz
        #define DELAY_MS_CNT    (203)   // TODO
        #define DELAY_10US_CNT  (10)    // TODO
    #elif (CONFIG_SYS_SCLK_DIV == 8)    // 3MHz / 2
        #define DELAY_MS_CNT    (102)   // TODO
        #define DELAY_10US_CNT  (5)     // TODO
    #elif (CONFIG_SYS_SCLK_DIV == 16)   // 3MHz / 4
        #define DELAY_MS_CNT    (51)    // TODO
        #define DELAY_10US_CNT  (3)     // TODO
    #elif (CONFIG_SYS_SCLK_DIV == 32)   // 3MHz / 8
        #define DELAY_MS_CNT    (26)    // TODO
        #define DELAY_10US_CNT  (2)     // TODO
    #elif (CONFIG_SYS_SCLK_DIV == 64)   // 3MHz / 16
        #define DELAY_MS_CNT    (13)    // TODO
        #define DELAY_10US_CNT  (1)     // TODO
    #endif
#else                                   /* LORC, 32KHZ */
        #define DELAY_MS_CNT    (1)     // TODO
        #define DELAY_10US_CNT  (1)     // TODO
#endif

#endif
